1. Technical Field
The present invention relates to an apparatus for driving a display panel which has capacitive light-emitting elements disposed in a matrix.
2. Background Art
Currently, display panels such as plasma display panels (hereinafter referred to as a PDP) or electroluminescence display panels (hereinafter referred to as an ELP) which include capacitive light-emitting elements have been commercially available as wall-hanging TVs.
FIG. 1 is a view schematically illustrating the configuration of a plasma display device which employs a PDP as such a display panel (e.g., see FIG. 3 in Japanese Patent Kokai No. 2002-156941 (Patent Document 1)).
With reference to FIG. 1, a plasma display panel or PDP 10 includes row electrodes Y1 to Yn and X1 to Xn arranged so that a pair of row electrodes X and Y adjacent to each other forms one display line of the screen. The PDP 10 also includes column electrodes Z1 to Zm which are formed to be orthogonal to the aforementioned pairs of row electrodes and which are associated respectively with the columns (the first to mth columns) of the screen with a dielectric layer and a discharge space (not shown) interposed therebetween. Note that there is formed a pixel cell responsible for a pixel at the portion of intersection of a pair of row electrodes (X, Y) and one column electrode Z.
A row electrode drive circuit 30 produces a sustain pulse to repetitively discharge only such a pixel cell as having residual wall charge for application to the row electrodes Y1 to Yn of the PDP 10. A row electrode drive circuit 40 produces a reset pulse to initialize the state of all the pixel cells, a scan pulse to sequentially select a display line on which pixel data is to be written, and a sustain pulse to repetitively discharge only such a pixel cell as having residual wall charge. The row electrode drive circuit 40 applies these pulses to the aforementioned row electrodes X1 to Xn.
A drive control circuit 50 converts an input video signal, e.g., to 8-bit pixel data on a pixel-by-pixel basis, which is in turn divided into a pixel data bit DB by bit digit. Then, on each display line basis, the drive control circuit 50 supplies pixel data bits DB1 to DBm to a column electrode drive circuit 20. Here, the pixel data bits DB1 to DBm are associated respectively with the first to mth columns and belong to each display line. Meanwhile, the drive control circuit 50 also produces switching signals SW1 to SW3 for supply to the column electrode drive circuit 20.
In response to the switching signals SW1 to SW3, each time one display line of (m) pixel data bits DB are supplied from the drive control circuit 50, the column electrode drive circuit 20 produces m pixel data pulses DP, each having a pulsed voltage associated with the logic level of each pixel data bit DB. The column electrode drive circuit 20 then applies the m pixel data pulses DP to the column electrodes Z1 to Zm, respectively. That is, in each predetermined pixel data cycle, the column electrode drive circuit 20 sequentially applies a display line of m pixel data pulses to the column electrodes Z1 to Zm, respectively, the (m) pixel data pulses being associated with each of the first to nth display lines. For example, the column electrode drive circuit 20 first applies the m pixel data pulses associated with the first display line respectively to the column electrodes Z1 to Zm during the first pixel data cycle. The column electrode drive circuit 20 then applies the m pixel data pulses associated with the second display line respectively to the column electrodes Z1 to Zm during the next second pixel data cycle. FIG. 2 is a view illustrating the internal configuration of such a column electrode drive circuit 20.
As shown in FIG. 2, the column electrode drive circuit 20 includes a power supply circuit 21 for producing a pulsed supply voltage of predetermined amplitude for application to a power supply line 2, and a pixel data pulse generation circuit 22 for producing the pixel data pulses DP in accordance with such a pulsed supply voltage.
As shown in FIG. 3, during each pixel data cycle CYC, the power supply circuit 21 produces a pulsed supply voltage having a peak voltage Va for application to the power supply line 2 in response to the switching signals SW1 to SW3 supplied from the drive control circuit 50. This is done to provide ON/OFF control to each of switching elements S1 to S3 in a sequence of drive steps G1 to G3. That is, in the drive step G1, the switching element S1 of the power supply circuit 21 is turned ON, thereby causing the charge stored on a capacitor C1 to be discharged. At this time, suppose that a SWZi of switching elements SWZ1 to SWZm in the pixel data pulse generation circuit 22 is in an ON state. In this case, a current caused by a discharge of the capacitor C1 flows into the column electrode Zi of the PDP 10 via the switching element S1, a coil L1, a diode D1, the power supply line 2, and the switching element SWZi. Thus, a parasitic load capacitance C0 of the column electrode Zi is charged to store charges thereon. Such a discharge operation of the capacitor C1 causes the power supply line 2 to increase in voltage gradually to twice a potential Vc at an end of the capacitor due to the resonance effect of the coil L1 and the load capacitance C0. Then, in the drive step G2, only the switching element S3 of the switching elements S1 to S3 is turned ON, thereby causing a DC voltage Va produced by a DC power supply B1 to be applied to the power supply line 2 via the switching element S3. At this time, the aforementioned voltage Va is at the peak voltage of the pulsed supply voltage as shown in FIG. 3. The voltage Va applied to the power supply line 2 causes a current to flow into the column electrode Zi of the PDP 10 via the switching element SWZi, allowing for charging the parasitic load capacitance C0 of the column electrode Zi to store charges thereon. Then, in the drive step G3, only the switching element S2 of the switching elements S1 to S3 is turned ON, thereby allowing the load capacitance C0 of the PDP 10 to initiate a discharge. Such a discharge results in a current flowing into the capacitor C1 via the column electrode Zi, the switching element SWZi, the power supply line 2, a coil L2, a diode D2, and the switching element S2. That is, the charge stored on the load capacitance C0 of the PDP 10 is transferred back to the capacitor C1 in the power supply circuit 21. At this time, the voltage on the power supply line 2 gradually decreases as shown in FIG. 3 in accordance with the time constant defined by the coil L2 and the load capacitance C0. Here, the gradually decreasing potential portion on the power supply line 2 as mentioned above is the trailing edge portion of the pulsed supply voltage.
The switching element SWZi (i: 1 to m) of the pixel data pulse generation circuit 22 is turned ON when the pixel data bit DB supplied is at logic level “1,” thereby causing the pulsed supply voltage on the power supply line 2 to be applied to the column electrode Zi. As such, the pixel data pulse DP of a high voltage is to be applied to column electrodes Zi. On the other hand, a switching element SWZi0 (i: 1 to m) of the pixel data pulse generation circuit 22 is turned ON when the pixel data bit DB is at logic level “0,” thereby causing a ground potential or “0” volt to be applied to the column electrode Zi. As such, the pixel data pulse DP of a low voltage is to be applied to the column electrode Zi.
FIG. 4 is a view illustrating how the column electrode drive circuit 20 operates to sequentially apply each of the pixel data pulses DP1i to DP6i associated respectively with the first to sixth display lines to the column electrode Zi (i: 1 to m), where only the column electrode Zi of the PDP 10 is shown for clarity. Note that FIG. 4 shows the operation to be performed when a bit train of pixel data bits DB associated respectively with the first to sixth display lines is [1, 1, 1, 1, 1, 0].
Here, the pixel data bits DB associated respectively with the first to fifth display lines are successively at logic level “1,” during which the switching element SWZi is in an ON state and the switching element SWZi0 is fixed in an OFF state as shown in FIG. 4. Accordingly, when the operation shown in FIG. 3 is repeated over pixel data cycles CYC1 to CYC5, those charges that could not be recovered in the drive step G3 of each of the CYC1 to CYC5 are gradually stored on the load capacitance C0 of the PDP 10. As a result, the pulsed supply voltage applied to the power supply line 2 gradually decreases in its resonance amplitude V1 as shown in FIG. 4 while being maintained at its maximum potential Va. Thus, the charge/discharge operations that would be otherwise caused by the aforementioned resonance effect will not occur, thereby suppressing reactive power.
Then, when the pixel data bit DB at logic level “0” associated with the sixth display line is supplied in the pixel data cycle CYC6 next to the pixel data cycle CYC5, the aforementioned switching element SWZi switches to an OFF state and the switching element SWZi0 to an ON state. The switching element SWZi0 being switched to the ON state causes the column electrode Zi to be connected to the ground, resulting in the voltage on the column electrode Zi being changed to 0 volt. However, as shown with EG in FIG. 4, a sudden change in the voltage on the column electrode Z from a relatively high potential to 0 volt would likely cause a high level noise and malfunction of the drive circuit.